As the size of integrated circuits shrinks, the number of devices within an integrated circuit has risen. For example, a rule of thumb commonly called Moore's Law states that the number of transistors in a state of the art integrated circuit generally doubles every eighteen months. For many years this rule of thumb has generally been true. Thus, the increase in the number of cells within an integrated circuit has grown exponentially rather than linearly. Obviously, over the past several years the number of cells within a single integrated circuit has virtually exploded.
This tremendous and rapid increase in the number of active devices within an integrated circuit has come about as a result of innovation and changes in the way that the devices are designed and fabricated. Thus, many different issues have been overcome in accomplishing this increase in the capacity of integrated circuits. At the same time, however, this increase in the complexity and capacity of integrated circuits has created new challenges in regard to other aspects of integrated circuit fabrication, such as testing.
Integrated circuits typically receive a wide variety of testing throughout the fabrication process, both to ensure that the processes used to fabricate the integrated circuits are in control, and also to ensure that the structures formed by the various processes have the proper characteristics. Most of the tests performed during the fabrication process look at only an extremely narrow range of characteristics, which tend to be pertinent only to the step in the fabrication process that was most recently completed. This type of testing is generally referred to as inline testing herein. As alluded to above, inline testing is typically performed throughout the front end fabrication processes of the integrated circuits.
However, there are typically two different instances where a large battery of tests are performed on the integrated circuits, to ensure that the integrated circuit as a whole functions in the desired manner. The first of these comprehensive tests is performed at the end of front end processing, and is commonly called wafer sort. It is so called because the integrated circuits have been processed in wafer form up to this point in the fabrication process. The second of these tests is performed at the end of back end processing, and is commonly called final test. During back end processing the integrated circuits have been diced and packaged, and are then tested as completed devices.
Another type of test typically performed on integrated circuits is known as stress testing. Stress testing of integrated circuits is often used to either eliminate or at least decrease the level of burn in testing required. During stress testing, the voltage level applied to the integrated circuit is elevated past the specification limits for a given length of time to see whether such a voltage impairs the integrated circuit. This is typically known as enhanced voltage stress testing. Dynamic voltage stress testing can be performed either in addition to or in place of enhanced voltage stress testing. During dynamic voltage stress testing, the applied voltage is varied from a high value to a low value over a period of time, again to determine whether such a voltage shift impairs the integrated circuit. Although stress testing reduces the need for the expensive and time consuming burn in, it is itself a rather lengthy test, and therefore appreciably adds to the cost of an integrated circuit.
Because integrated circuits have so many more active devices than in times past, the time required for stress testing, and wafer sort and final test, jointly and severally referred to as comprehensive testing herein, has likewise increased exponentially. Because this required length of time adds an unacceptable labor and equipment expense to the fabrication costs of the integrated circuits, there is continual pressure to discover and implement alternate procedures for testing the integrated circuits, which procedures are preferably less time consuming but at least adequately thorough.
What is needed, therefore, is a test methodology by which an integrated circuit can be adequately tested within an amount of time that is less than that of prior art techniques.